Coefficient of Thermal Expansion (CTE) Testing for IC Substrates: Thermal Stress Evaluation and Meas

Coefficient of thermal expansion (CTE) measurement is a critical reliability test for IC substrates, quantifying how the package substrate deforms under thermal loading and how much thermal stress develops between the silicon die, substrate, and printed circuit board. This technical article covers CTE testing principles, sample requirements, measurement methods such as thermomechanical analysis (TMA), applicable industry standards, and typical acceptance criteria for substrate qualification.

Technical Overview

An IC substrate (package substrate) serves as the electrical and mechanical interposer between the silicon die and the motherboard. Because the substrate is fabricated from organic materials such as bismaleimide triazine (BT) resin, epoxy resins, Ajinomoto build-up film (ABF), and glass-fiber reinforcement, it expands and contracts with temperature far more than the silicon chip it carries. The coefficient of thermal expansion (CTE) quantifies this dimensional change and is defined as the fractional change in length per unit change in temperature, typically expressed in ppm/°C (10⁻⁶/°C).

Thermal stress arises directly from CTE mismatch within the package stack. Silicon exhibits a CTE of approximately 2.6 ppm/°C, a typical BT or epoxy-glass substrate falls between 10 and 17 ppm/°C in the in-plane direction, and the PCB laminate ranges from 14 to 18 ppm/°C. During reflow assembly and subsequent thermal cycling, this mismatch produces shear strain in solder joints, tensile stress in low-k dielectric layers, warpage of the assembled package, and interfacial stress that can drive delamination between copper, solder mask, and dielectric layers.

Accurate CTE determination therefore underpins package design, material selection, and reliability prediction. Key measurement outputs include the CTE below the glass transition temperature (α1), the CTE above Tg (α2), the glass transition temperature itself, and the out-of-plane (Z-axis) expansion behavior, all of which are governed by recognized standards such as IPC-TM-650 2.4.24, IPC-4101, IPC-4103, ASTM E831, and ISO 11359-2.

Testing Samples

Bare Substrate Materials

Qualification testing is commonly performed on unpatterned laminate materials representing the substrate construction, including BT resin systems, high-Tg epoxy-glass cores, polyimide films, and cured build-up dielectric films. These samples isolate the intrinsic thermo-mechanical behavior of the composite without the influence of circuit patterns.

Patterned and Finished Substrates

Production substrates with etched copper traces, plated through-holes, microvias, and solder mask can also be tested to capture the effective CTE of the finished construction. Copper content, pattern density, and resin distribution measurably shift both in-plane and Z-axis expansion, so finished-article testing is valuable for design verification and lot acceptance.

Sample Preparation and Conditioning

• Specimen geometry: rectangular strips (typically 3–10 mm long, 2–5 mm wide) for in-plane measurement, or flat coupons (approximately 5 mm square) for Z-axis (thickness-direction) measurement, with thickness typically between 0.1 mm and 1.5 mm.
• Surface preparation: both faces of Z-axis specimens must be flat, parallel, and free of burrs or warpage to ensure uniform probe contact.
• Pre-conditioning: bake (commonly 105–125 °C for 2 hours) to remove absorbed moisture, then condition at 23 ± 2 °C and 50 ± 5% relative humidity before testing.
• Sample quantity: a minimum of three to five specimens per material and per orientation is recommended to characterize variability.
• Orientation marking: specimens must be labeled with machine direction (MD) and transverse direction (TD) because glass-fabric reinforcement makes in-plane CTE anisotropic.

Testing Items

A complete CTE characterization program for IC substrates typically includes the following measurement items:

• α1 — in-plane CTE below Tg (typically 25 °C to Tg), the value most relevant to solder joint stress during operation.
• α2 — in-plane CTE above Tg, which indicates how rapidly the softened resin expands and reflects crosslink density and cure state.
• Z-axis (out-of-plane) CTE, critical for plated through-hole integrity, microvia reliability, and solder mask adhesion; Z-axis values are typically 30–60 ppm/°C below Tg and rise sharply above Tg.
• Glass transition temperature (Tg) determined from the inflection point of the expansion curve, per IPC-TM-650 2.4.24C.
• Time to delamination (T260 / T288 / T300), frequently measured in the same TMA run at isothermal 260 °C, 288 °C, or 300 °C to assess laminar integrity during lead-free reflow.
• ΔCTE relative to silicon, a derived design parameter used to estimate thermo-mechanical strain in die-attach and bump structures.
• Pressure-dependent thickness change and cure shrinkage, optional measurements for build-up film evaluation.

Testing Methods

Thermomechanical Analysis (TMA) — Primary Method

TMA is the industry-standard technique for organic substrate CTE determination. A specimen is placed on a quartz platform and a low-mass quartz expansion probe applies a small static force (typically 0.05–0.2 N) on the top surface. A programmed furnace heats the specimen, generally at 5 °C/min from room temperature (or −50 °C) up to 260–300 °C under nitrogen purge, while a high-resolution displacement sensor records dimensional change. The CTE is computed from the slope of the dimension-versus-temperature curve using the mean specimen dimension over the analysis interval, following ASTM E831 and IPC-TM-650 2.4.24.

Dilatometry

Push-rod dilatometers accommodate larger specimens and higher temperature ranges. They are useful for verifying TMA results and for materials research on new resin systems, though their displacement resolution is generally lower than TMA for thin substrate coupons.

Strain Gauge Method

Bonded high-precision foil or capacitive strain gauges measure in-plane thermal strain directly on finished substrates or assembled packages. This method captures the effective CTE of a real, patterned article and can be applied across multiple thermal cycles to reveal non-linear or hysteretic behavior.

Optical Full-Field Methods

• Digital Image Correlation (DIC): full-field in-plane strain mapping during heating, suitable for characterizing local CTE variation across dense circuit regions.
• Moiré interferometry and shadow moiré: high-sensitivity warpage and deformation measurement of substrates and assembled packages, directly supporting coplanarity and warpage budgets.
• Thermoreflectance and laser interferometry: non-contact thickness change measurement for thin films and build-up layers.

Measurement Workflow and Quality Controls

• Instrument calibration against a certified reference material (e.g., aluminum or quartz standard) before each test campaign.
• Baseline run with an empty platform or reference quartz to subtract system expansion.
• Verification of specimen contact, flatness, and load stability at the start of each run.
• Analysis of two heating ramps when thermal history matters: the first run removes residual stress and moisture effects, while the second run provides the reported intrinsic CTE.
• Reporting of test direction, temperature interval, heating rate, Tg, and specimen conditioning alongside the CTE value, as required for interlaboratory comparability.

Applications

CTE measurement data directly support nearly every stage of the IC substrate and packaging lifecycle:

• Package design and simulation: CTE values feed finite-element models used to predict solder joint fatigue life, die stress, and package warpage for flip-chip BGA, chip-scale packages, and system-in-package products.
• Material qualification: laminate and build-up film suppliers and substrate manufacturers use α1, α2, Tg, and Z-axis CTE data to qualify new resin systems against IPC-4101/4103 specification sheets.
• Incoming inspection and statistical process control: routine TMA testing monitors lamination cure, resin content, and batch-to-batch consistency.
• Reliability assessment: CTE mismatch data are correlated with temperature-cycle testing (for example, −55 °C to +125 °C per JEDEC JESD22-A104) to project field lifetime.
• Failure analysis: anomalous α2, depressed Tg, or short time-to-delamination identifies under-cured resin, moisture uptake, or interfacial contamination as root causes of cracking and delamination.
• Advanced packaging development: 2.5D/3D integration, high-density fan-out, and ABF-based FCBGA substrates demand tightly controlled, low-CTE materials, making precision CTE data essential for next-generation product roadmaps.

FAQ

What is a typical CTE target for an IC substrate?

In-plane CTE of 10–17 ppm/°C is common for BT and epoxy-glass cores, chosen to sit between silicon (about 2.6 ppm/°C) and the PCB (about 14–18 ppm/°C) so that solder joint strain is balanced. Low-CTE cores near 6–10 ppm/°C are used for large-body flip-chip packages to limit die stress.

Why is Z-axis CTE usually much higher than in-plane CTE?

Glass-fabric reinforcement constrains expansion in the X and Y directions but not through the thickness, where neat resin dominates. High Z-axis CTE stresses plated through-holes and microvias during reflow, which is why Z-axis values and T260/T288 delamination resistance are closely monitored.

What temperature range and heating rate are used?

A typical TMA program runs from 25 °C (or −50 °C) to 260–300 °C at 5 °C/min under nitrogen, consistent with IPC-TM-650 2.4.24 and ASTM E831. Slower rates or stepwise isothermal methods may be used when higher resolution near Tg is required.

How does TMA-measured Tg differ from DSC and DMA values?

TMA detects Tg from the change in expansion slope, DSC from the change in heat capacity, and DMA from the peak in mechanical damping. Values differ systematically, so the test method must always be cited when comparing specifications.

How many specimens should be tested?

At least three specimens per orientation and per construction are recommended. Glass-fabric anisotropy, copper distribution, and local resin richness produce real specimen-to-specimen variation, so replicate testing is essential for meaningful acceptance decisions.

What acceptance criteria are commonly applied?

Criteria are set by the applicable IPC-4101/4103 slash sheet or the customer drawings, commonly specifying maximum α1 and α2, minimum Tg, Z-axis CTE limits, and minimum time to delamination at 260 °C or 288 °C for lead-free-compatible substrates.