Thermal Expansion Testing of Semiconductor Package Substrates: CTE Measurement Methods and Reliabili

Thermal expansion testing of semiconductor package substrates measures the coefficient of thermal expansion (CTE), the single most influential material parameter governing solder joint fatigue, warpage behavior, and long-term interconnect integrity in BGA, flip-chip, and chip-scale packages. Accredited third-party laboratories perform these experiments using thermomechanical analysis and dilatometry in accordance with ASTM, ISO, IEC, and EN standards. This article outlines the test samples, measured parameters, test methods, acceptance criteria, and typical applications of substrate CTE evaluation.

Technical Overview

A semiconductor package substrate, also known as an IC substrate or interposer, is the thin, high-density circuit carrier that mechanically supports the silicon die and redistributes its fine-pitch connections to the board-level printed circuit board. During reflow soldering, burn-in, and repeated power cycling, the package undergoes significant temperature excursions, and every material layer expands at a different rate. Silicon expands at only about 2.6 to 3.0 ppm/°C, while a standard glass-epoxy circuit board expands at 14 to 17 ppm/°C, so the substrate must act as a compliant thermal-expansion bridge between the two.

Thermal expansion experiments quantify this behavior. A specimen is heated at a controlled rate while its dimensional change is recorded continuously, and the slope of the dimension-versus-temperature curve yields the coefficient of thermal expansion. For organic substrates the result is divided into alpha-1 (below the glass transition temperature) and alpha-2 (above Tg), because crosslinked polymers soften dramatically once the glass transition is exceeded. Typical specifications require an in-plane CTE of 6 to 12 ppm/°C for flip-chip substrates, 12 to 17 ppm/°C for wire-bond BGA substrates, and a through-thickness CTE below approximately 60 ppm/°C up to Tg in order to protect plated through-holes and stacked microvias from cyclic fatigue.

Testing Samples

Organic Rigid Substrates

Bismaleimide-triazine (BT) and epoxy-glass laminate substrates used for BGA, QFN, and memory packages. Coupons are cut from production panels, typically as squares of 4 to 10 mm or strips of defined width, and are measured at full production thickness so that core, copper, and dielectric layers are all represented.

Build-Up and Fine-Line Substrates

Substrates built with photosensitive dielectric films and laser-drilled microvias for flip-chip and high-performance processor packages. Core material, build-up film, and the finished composite may be tested separately to construct a complete CTE model for warpage simulation.

Flexible and Rigid-Flex Substrates

Polyimide-film substrates used in chip-on-film, flex-BGA, and camera module assemblies. These samples are strongly anisotropic and hygroscopic, so they are baked to remove absorbed moisture and conditioned in a standard laboratory atmosphere before measurement.

Ceramic Substrates

Alumina (approximately 6.5 to 7.2 ppm/°C), aluminum nitride (approximately 4.2 to 4.8 ppm/°C), and silicon nitride substrates for power modules and RF applications. Their very low expansion requires high-resolution dilatometry or a calibrated TMA run with reference-sample correction.

Raw Material Coupons

Copper-clad laminates, prepreg sheets, build-up resin films, solder mask coatings, and encapsulation compounds submitted for incoming inspection, material qualification, or comparative material selection studies.

Testing Items

A complete thermal expansion experiment on a semiconductor substrate reports the following parameters:

• Alpha-1: coefficient of thermal expansion below Tg, in the x, y, and z directions
• Alpha-2: coefficient of thermal expansion above Tg, where organic materials expand two to five times faster
• Glass transition temperature determined by TMA, including the step change in expansion rate at the transition
• Total percentage of expansion over a specified window, for example 50 °C to 260 °C
• Through-thickness (z-axis) expansion, which controls plated-hole and microvia copper fatigue
• Dimensional stability and expansion hysteresis after repeated thermal cycles

Acceptance limits are normally defined by the package design house based on die size, solder joint geometry, and the temperature range of the intended service environment, and they are verified during incoming material inspection at accredited third-party laboratories.

Testing Methods

Thermomechanical Analysis (TMA)

The primary method for substrate CTE, performed per ASTM E831, ISO 11359-2, and the European adoption EN ISO 11359-2. The specimen rests on a quartz platform beneath a low-mass probe applying 5 to 20 mN of force. The furnace ramps at 3 to 5 °C per minute from room temperature, or from -50 °C for low-temperature data, up to 260 to 300 °C under a nitrogen purge. Alpha-1, alpha-2, and Tg are extracted from a single scan by linear regression over defined temperature segments, with the first heating ramp sometimes discarded as thermal conditioning of the specimen.

Quartz Dilatometry

Performed per ASTM E228 and ASTM D696, a long specimen of 50 to 125 mm is placed inside a quartz tube and its expansion is transmitted through a pushrod to a displacement sensor. This method offers excellent precision for low-CTE ceramics and for in-plane expansion measurements of laminate materials where the finest resolution is required.

In-Plane Optical and Strain-Gauge Techniques

Foil strain gauges bonded in the x and y directions, digital image correlation, or laser interferometry measure in-plane CTE and full-field warpage of finished substrates under realistic reflow-like temperature profiles, complementing the point-contact data from TMA and dilatometry.

Specimen Preparation and Conditioning

Specimens must be flat with parallel faces, free of burrs, and stress-relieved where necessary. Laminate-level tests require balanced copper patterns to avoid asymmetric reinforcement effects. Moisture-sensitive samples are baked and then conditioned at 23 °C and 50% relative humidity, and moisture content is documented, because absorbed water depresses the apparent Tg and inflates the measured expansion.

Applications

• Package design and material selection, where measured CTE values feed finite-element warpage models and solder joint stress simulations
• Reliability qualification, correlating CTE data with air-to-air temperature cycling, typically between -55 °C and 125 °C, to predict interconnect fatigue life
• Supplier quality control and incoming inspection of laminates, prepregs, and build-up films against datasheet limits
• Failure analysis, detecting CTE drift or Tg degradation after moisture absorption, reflow exposure, or over-temperature events
• Advanced packaging development for glass-core substrates, silicon interposers, low-CTE prepregs, and low-expansion alloy cores that push in-plane CTE closer to that of silicon

FAQ

What CTE value is considered acceptable for an IC substrate?

It depends on the package architecture. Flip-chip substrates generally target 6 to 12 ppm/°C in-plane to limit solder joint shear strain, wire-bond BGA substrates typically fall between 12 and 17 ppm/°C, and ceramic substrates used for power devices range from about 4 to 7 ppm/°C to closely match silicon and direct-bonded copper layers.

Why are alpha-1 and alpha-2 reported separately?

Organic substrate materials are glassy below Tg and rubbery above it, so their expansion rate roughly doubles or triples after the transition. Peak reflow temperatures exceed Tg, meaning alpha-2 dominates the stress state during the most damaging part of the assembly process and must therefore be controlled independently.

What temperature range should the test cover?

The range must bracket all processing and service temperatures, typically from room temperature or -50 °C up to 260 to 300 °C, so that behavior beyond the highest lead-free reflow peak is captured and the transition region is fully defined.

How is TMA-derived Tg different from DSC-derived Tg?

TMA detects Tma through the change in expansion rate, which is sensitive to mechanical softening, while DSC per ISO 11357 or GB/T 19466.2 detects the heat-capacity step. TMA values are usually slightly lower, and the two results should not be mixed when comparing against a specification.

Why is through-thickness CTE so important?

Z-axis expansion is typically two to three times larger than in-plane expansion because polymer expansion is constrained in x and y by glass weave and copper. Every thermal cycle forces plated hole walls and stacked microvias to stretch and contract, making z-axis CTE the controlling parameter for via cracking and inner-layer delamination.